1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having nonvolatile memory cells to which a voltage is applied to read out data stored therein.
2. Description of the Background Art
Conventionally, various types of flash memory have been proposed, one of which is of a so-called “multi-valued memory cell”. The “multi-valued memory cell” may be a nonvolatile memory cell which can store two kinds of data and output the stored data in different directions. The flash memory may often include an array of multi-valued memory cells aligned in the form of matrix. Technique employed for such flash memories is disclosed by, for example, U.S. Patent Application Publication Nos. US2005/0265107 A1 to Tanaka and US2006/0239059 A1 to Murata.
The memory cell array circuit taught by Murata is formed into a plurality of sub-blocks, each of which includes eight drain selectors, each of which includes an N (Negative)-channel MOS-FET (Metal-Oxide Semiconductor Field-Effect Transistor), i.e. NMOS-FET. Each NMOS-FET has its source electrode connected to a common power supply line and its gate electrode connected to a corresponding drain select line. Each drain selector, made up of an NMOS-FET, has its drain electrode connected to the source electrode of a corresponding source selector. As described above, the wiring between the drain electrode of the drain selector and the source electrode of the source selector functions as a bit line. The bit lines are also connected to memory cells described below. The source selectors also include NMOS-FETs. The plurality of bit lines is arranged to intersect a plurality of word lines at the respective cross points of the matrix.
The memory cells are multi-valued memory cells, each of which is capable of storing two pieces of data different between two directions. In the vertical direction of the matrix, there are arranged N+1 memory cells between the drain electrode of the drain selector and the source electrode of the source selector, where N is a natural number. In the horizontal direction of the matrix, there is arranged a memory cell in an area formed between the drain selectors adjacent to each other. In the column direction of the matrix, the memory cells have the source electrode thereof commonly connected to the same bit line and the drain electrode thereof commonly connected to another bit line. Thus, each memory cell has its source electrode connected to the drain electrode of another memory cell adjacent thereto in the horizontal direction by the bit line. The memory cells have the gate electrode thereof connected to a word line wired in the horizontal direction. The arrangement of the memory cells provides the N+1 word lines.
Every four of the source selectors form a set of source selectors, and the four source select lines are connected to the respective gate electrodes of different sets of four source selectors. The source selectors have the drain electrodes thereof connected to multiplexers, each of which includes a pair of NMOS-FETs. The pair of NMOS-FETs in each multiplexer have the gate electrodes thereof commonly interconnected to each other and connected to a column select line. The pair of NMOS-FET in each multiplexer has the drain electrodes connected to respective sense amplifiers so that the odd-numbered, in other words, left NMOS-FET in each multiplexer has its drain electrode connected to a sense amplifier different from one connected to the even-numbered NMOS-FET.
Next, the principle operation of the multi-valued memory cell will be described. This multi-valued memory cell is a nonvolatile memory cell having the MOS-FET structure. The multi-valued memory cell has a P (Positive)-well region formed in a semiconductor substrate. On the surface of the P-well region, a gate electrode is formed with a gate insulating film intervening. On the sidewall of the gate electrode, there is formed a memory entity, or entity, composed of a nitride film. In the surface of the P-well regions, N-type diffusion regions are formed to partly extend below the memory entity. These diffusion regions alternatively function as a source or a drain electrode in response to a voltage applied thereto.
In the write operation to the multi-valued memory cell, electrons are injected into each memory entity to write data. In order to write the data into the left memory entity, the right diffusion region is set as a source electrode, and the left diffusion region is set as a drain electrode. The diffusion region and the P-well region are biased to 0V (volt), and the diffusion region and the gate electrode are biased to +5V. By this biasing, the inversion layer extends from the diffusion region adjacent to the source electrode, but is pinched off before reaching the diffusion region adjacent to the drain electrode in the multi-valued memory cell. The electrons are accelerated by the high electric field from the pinch-off point to the diffusion region, becoming so-called hot electrons.
The hot electrons are injected into the left memory entity to write the data. On the other hand, no hot electrons are generated in the vicinity of the right memory entity, so that no data are written. In order to write data into the right memory entity, the left diffusion region can be set as the source electrode and the right diffusion region as the drain electrode.
In the readout operation from the multi-valued memory cell, in order to read the data stored in the left memory entity, the left and left diffusion regions are set as the source and drain electrodes, respectively, to make the multi-valued memory cell operative. The diffusion region and P-well region are biased to 0V, the diffusion region is biased to +1.8V, and the gate electrode is biased to +2V. In this case, if no electrons are stored in the left memory entity, a drain current readily flows to the multi-valued memory cell. By contrast, if electrons are stored in the left memory entity, hardly any inversion layer forms therebelow, so that hardly any drain current flows. Accordingly, the data stored in the left memory entity can be read out by detecting the drain current. In order to read out the data stored in the right memory entity, the right and left diffusion regions are set as the source and drain electrodes, respectively, to render the multi-valued memory, cell operative.
In addition, the operation of erasing the data stored in the multi-valued memory cell will be described. In order to erase the data stored in the left memory entity, the PN (Positive-Negative)-junction between the left diffusion region and P-well region is reversely biased by positively biasing the left diffusion region to +5V and the P-well region to 0V. In addition, the gate electrode is negatively biased to −5V. The right diffusion region is biased to 0V. The potential gradient at the PN-junction thereby becomes especially steep in the vicinity of the gate electrode due to the negatively biased gate electrode. This induces band-to-band tunneling and generates hot holes on the P-well region side of the PN-junction. The hot holes are attracted towards the negatively biased gate electrode and injected into the left memory entity, thus erasing the data stored therein. In order to erase the data stored in the right memory entity, the potentials applied to the left and right diffusion regions are opposite to what are described above.
As described above, in the multi-valued memory cell adapted for storing two bits, the memory entities are formed on the left and right sidewalls of the gate electrode, and the left and right diffusion regions corresponding to the two memory entities are set as a source and a drain electrode, respectively, or as a drain and a source electrode, respectively, thus using the multi-valued memory cell to store two bits of data.
In an array of multi-valued memory cells aligned in a lattice-like structure, when data are to be read out from the left of a multi-valued memory cell in the third column toward another multi-valued memory cell adjacent thereto at the right in the (N−1)th line of a certain sub-block, and at the same, time data are read out from the right of a multi-valued memory cell in the first column toward another multi-valued memory cell adjacent thereto at the left in the (N−1)th line of another sub-block, the voltages will be applied in the following manner.
The word line in the (N−1)th line is set to its logical “1”, and at the same time, the first and third drain select lines are set to the logical “1” thereof. The first and third drain selectors in each sub-block are thereby turned on, in other words, made conductive.
At the same time, the third source select line is set to its logical “1”. By this setting, for example, the third and seventh source selectors in a certain sub-block are turned on. At the same time, the column select line is set to its logical “1” so as to select the multiplexers having drain outputs supplied from the first and seventh source selectors. The NMOS-FETs in the selected multiplexers are thereby turned on.
In the memory cell device, in order to turn on the multi-valued memory cell in the third column of the (N−1)th line in a specific sub-block in the cell array, the drain selector in the third column and the multi-valued memory cell at the intersection of the (N−1)th line and the third column are turned on, thereby enabling a current coming from a common power supply line to flow from the left to the right of the multi-valued memory cell and further to flow to the source selector in the third line or row over the bit line at the right of the multi-valued memory cell. This current flows into the sense amplifier through the NMOS-FET of the multiplexer connected to the source selector in the third row. In the memory cell device, the sense amplifier determines a logical “1” by the current flowing thereinto.
In order to turn off the multi-valued memory cell at the intersection of the (N−1)th row and the third column, the multi-valued memory cell is made non-conductive to disable a sufficient current from the common power supply line from flowing into the bit line through the multi-valued memory cell. Thus, the sense amplifier determines a logical “0”.
Similarly, in order to turn on the multi-valued memory cell at the intersection of the (N−1) throw and the first column, the drain selector in the first column and the multi-valued memory cell at the intersection of the (N−1) throw and the first column are turned on, thereby enabling a current from the common power supply line to flow from the right to the left of the multi-valued memory cell and to further flow to the source selector in the third row over the bit line at the left of the multi-valued memory cell. In this case, this current also flows into the sense amplifier through the NMOS-FET of the multiplexer connected to the source selector in the third row. In the memory cell device, the sense amplifier determines a logical “1” by the current flowing thereinto.
Similarly, in order to turn off the multi-valued memory cell at the intersection of the (N−1) throw and the first column, the multi-valued memory cell is made non-conductive to disable a sufficient current from flowing into the bit line at the left of the multi-valued memory cell. Thus, the sense amplifier determines a logical “0”.
Well, a semiconductor memory device to which the above-described method for applying the voltage is applied aims at avoiding an increase in area of the memory cell array as far as possible while minimizing the influence on the readout operation by a leakage current, in other words, an interferential current flowing through one or ones, especially having data, of binary “1” stored, of the other multi-valued memory cells connected to the selected (N−1)th word line. However, even applying this method cannot completely negate the influence of the interferential current.
If data to be read out from the left to the right of the multi-valued memory cell at the intersection of the (N−1)th row and the third column are of the off state, i.e. logical “0”, and data to be read out from the right to the left of the multi-valued memory cell at the intersection of the (N−1)th row and the first column are of the on state, i.e. logical “1”, while the four memory cells therebetween are minimum in on-resistance component in both right and left directions to have the logical “1”, then a current from the drain selector in the first row flows not only to the left bit line through the multi-valued memory cell at the intersection of the (N−1)th row and the first column but also to the bit line at the right of the multi-valued memory cell at the intersection of the (N−1)th row and the third column through the other four multi-valued memory cell connected to the (N−1)th word line as a small interferential current. The memory cell array is affected by the interferential current flowing thereinto to decrease its read out speed or to cause the sense amplifier to be virtually increased in threshold current from its actual value. These phenomena, from the viewpoint of power supply voltage and timing, deteriorate the access time, and hence access margin, to a remarkable extent.
As described above, the conventional semiconductor memory devices have a problem such that an interferential current flows to other multi-valued memory cells connected to a selected word line to exert a bad influence on the fast readout operation or operational margin. Especially, such a phenomenon can be almost negligible in the technique for storing one bit of data per direction of a multi-valued memory cell, but not in a memory cell device including multi-valued memory cells storing two or more bits of data per direction.
For such a problem, the solution taught by Tanaka may be effective, which discloses a semiconductor memory device having a memory cell array employing a virtual ground line system and formed in a hierarchical bit line structure including main and sub-bit lines. Tanaka discloses a solution for reducing a variation in wiring capacitance of the main bit lines to enable the fast readout.
The hierarchical bit line structure is advantageous in fast reading out data stored in, for example, a memory cell array for use in a semiconductor memory device of large storage capacity. The memory cell array in a hierarchical bit line structure is sectioned into a plurality of sub-blocks in its column direction. The bit lines in each sub-block are set as the sub-bit lines. A set of plural sub-bit lines in each sub-block is connected to the main bit line through a sub-block select transistor.
In order to select a memory cell, a main bit line is used as a bit line for the selection. Furthermore, a sub-bit line to be connected to the selected main bit line is selected by the sub-block select transistor.
Specifically, in FIG. 6 and paragraphs 0007 to 0012 of Tanaka, it is disclosed that, in order to prevent a detour outflow current corresponding to the interferential current from occurring, a charging potential is supplied to the sub-bit lines in another sub-block adjacent to the sub-block including the selected memory cell.
However, since the solution by Tanaka uses the main bit line for the source and drain electrodes of a multi-valued memory cell to be read, a bias for use in eliminating the interferential current has to be applied by a main bit line further adjacent thereto. As a result, between the sub-bit line used for readout and the biased main bit line, a bit line exists which may cause floating, thus enabling an interferential current to flow until this bit line is charged, which is also problematic. Because of the problems, it is indeed difficult in the solution by Tanaka to, solve the problems.